Field of the Disclosure
This disclosure relates generally to the use of memory in an information processing system and, more specifically, to the use of a cache in an information processing system.
Description of the Related Art
Different types of memory require different amounts of time to retrieve data from them. Often, a type of memory capable of storing a large amount of data may require a relatively long time to access the data, while a type of memory that provides a relatively shorter time to access data may be impractical to implement on a scale sufficient to store a large amount of data, for example, due to size constraints of the faster memory. One well-known technique that is utilized to improve data access time while still allowing access to a large amount of data is to use a cache to store frequently accessed data. A cache is a relatively small amount of fast access memory that is mapped to the same address as a main memory having a slower access time. When information stored at a cache represents the most-current copy it is referred to as valid, and is accessed from the cache at the faster access time of the cache rather than from the main memory at the slower access time. When a cache does not store a valid copy of data being requested, the data is accessed from main memory at the slower access time of main memory. It will be appreciated, that information loaded from slower main memory can be loaded into the cache for subsequent accesses.
Data retrieved from main memory that are stored in a cache are generally referred to as being stored in cache lines. A cache line is portion of the cache memory that represents a number of contiguous memory locations, generally a power of two bytes in length. A cache line includes cache entries corresponding to such memory locations, such that a cache entry is an example of a portion of a cache line. Cache lines are aligned in main memory on a multiple of the cache line length. Each valid cache line stores a sequence of data from a target memory having a common address portion, referred to as a tag. In the cache, each cache line has an associated tag field where the tag of a cache line is stored to distinguish addresses of the information stored at the tag line from addresses associated with all other cache lines. To determine whether or not requested data is in cache, a tag lookup is performed at the cache to determine if a valid cache tag exists that matches a corresponding address portion of the requested data. A cache access wherein a tag lookup is performed is referred to as a normal tag-based access.
Various cache configurations impose various levels of constraint on where cache data from a particular main memory address may be stored. For example, a direct mapped cache allows only a single cache entry to be used for data from a particular main memory address, a fully associative cache allows data from a particular main memory address to be stored anywhere in the cache, and a set-associative cache allows data from a particular main memory address to be stored in any one of a particular number of locations in the cache. For example, a two-way set-associative cache allows data from a particular main memory address to be stored in any one of two cache locations. In order to determine whether data for a particular address is available in either of the two ways of the two-way set associative cache, two sets of tag look-ups need to be performed.
Caches thus provide improved access time and latency, but the necessity of performing tag lookups, especially for the more efficient set-associative cache organizations, expends an undesirable amount of energy. There is thus a need for a memory organization which provides the access benefits of a cache but with substantially reduced energy costs.
The use of the same reference symbols in different drawings indicates similar or identical items.